HD64F38602R Datasheet, PDF (535/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
Section 9 Timer B1
148 Modified
Figure 9.2 Timer B1 Initial Setting
Flow
Cancel the module standby mode of timer B1
*¹
Set counter function with bit TMB17
in TMB1 and counter clock with bits
TMB12 to TMB10 in TMB1
(bit TMB16 must be cleared to 0
when writing to these bits)
Section 11 Realtime Clock (RTC) 193
11.3.7 Clock Source Select
Register (RTCCSR)
Modified
Bit Bit Name Description
3 RCS3
2 RCS2
1 ^RCS1
0 ^RCS0
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φ /4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
W
1001 to 1111: Setting prohibited
11.4.1 Initial Settings of Registers 196
after Power-On
11.5 Interrupt Sources
198
11.6.2 Note when Using RTC 199
Interrupts
Modified
The RTC registers that store second, minute, hour, and
day-of-week data, control registers, and interrupt
registers are not reset by a RES input, or by a reset
source caused by a watchdog timer.
Modified
… When using an interrupt, set the IENRTC (RTC
interrupt request enable) bit in IENR1 to 1 last after
other registers are set.
Added
Rev. 3.00 May 15, 2007 Page 503 of 516
REJ09B0152-0300