HD64F38602R Datasheet, PDF (11/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
Notes on Board Design ........................................................................................... 74
Definition of Oscillation Stabilization Wait Time .................................................. 74
Note on Subclock Stop State................................................................................... 76
Note on the Oscillation Stabilization of Resonators ............................................... 76
Note on Using Power-On Reset .............................................................................. 76
Note on Using On-Chip Emulator .......................................................................... 76
Section 5 Power-Down Modes ............................................................................77
5.1 Register Descriptions ........................................................................................................... 78
5.1.1 System Control Register 1 (SYSCR1) .................................................................... 78
5.1.2 System Control Register 2 (SYSCR2) .................................................................... 80
5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ..................................... 81
5.2 Mode Transitions and States of LSI..................................................................................... 83
5.2.1 Sleep Mode ............................................................................................................. 87
5.2.2 Standby Mode ......................................................................................................... 88
5.2.3 Watch Mode............................................................................................................ 88
5.2.4 Subsleep Mode........................................................................................................ 89
5.2.5 Subactive Mode ...................................................................................................... 89
5.2.6 Active (Medium-Speed) Mode ............................................................................... 90
5.3 Direct Transition .................................................................................................................. 91
5.3.1 Direct Transition from Active (High-Speed)
Mode to Active (Medium-Speed) Mode ................................................................. 91
5.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode................. 92
5.3.3 Direct Transition from Active (Medium-Speed)
Mode to Active (High-Speed) Mode ...................................................................... 92
5.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode ........... 93
5.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode................. 93
5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........... 94
5.3.7 Notes on External Input Signal Changes before/after Direct Transition................. 95
5.4 Module Standby Function.................................................................................................... 96
5.5 On-Chip Oscillator and Operation Mode ............................................................................. 96
5.6 Usage Notes ......................................................................................................................... 97
5.6.1 Standby Mode Transition and Pin States ................................................................ 97
5.6.2 Notes on External Input Signal Changes before/after Standby Mode..................... 97
Section 6 ROM ....................................................................................................99
6.1 Block Configuration........................................................................................................... 100
6.2 Register Descriptions ......................................................................................................... 101
6.2.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 101
6.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 102
Rev. 3.00 May 15, 2007 Page xi of xxxii