HD64F38602R Datasheet, PDF (332/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Reception: Figure 15.7 shows an example of the SSU operation for reception. In
serial reception, the SSU operates as described below.
When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the
SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is
set as a master device, it outputs a receive clock and starts reception by performing dummy read
on SSRDR.
After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in
SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the
RDRF bit is automatically cleared to 0.
When the SSU is set as a master device and reception is ended, received data is read after setting
the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped.
After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if
SSRDR is read while the RE bit is set to 1, received clock is output again.
When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an
overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1,
reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before
reception.
Figure 15.8 shows a sample flowchart for serial data reception.
SSCK
SSO
RDRF
Bit 0
One frame
Bit 7
Bit 0
One frame
Bit 7
Bit 0
Bit 7
RSSTP
LSI operation
RXI generated
RXI generated
RXI generated
User
processing
Dummy read
on SSRDR
Read data in SSRDR
Set RSSTP to 1Read data
in SSRDR
Figure 15.7 Example of Operation in Data Reception (MSS = 1)
Rev. 3.00 May 15, 2007 Page 300 of 516
REJ09B0152-0300