HD64F38602R Datasheet, PDF (384/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 17 A/D Converter
Initial
Bit Bit Name Value R/W Description
3
CH3
2
CH2
1
CH1
0
CH0
0
R/W Channel Select 3 to 0
0
R/W Select the analog input channel.
0
R/W 00xx: No channel selected
0
R/W 0100: AN0
[Legend] x: Don't care.
0101: AN1
0110: AN2
0111: AN3
1000: AN4
1001: AN5
101x: No channel selected
11xx: No channel selected
The channel selection should be made while the ADSF
bit is cleared to 0.
17.3.3 A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit Bit Name
7
ADSF
6
LADS
5 to 0 
Initial
Value R/W Description
0
R/W When this bit is set to 1, A/D conversion is started.
When conversion is completed, the converted data is
set in ADRR and at the same time this bit is cleared to
0. If this bit is written to 0, A/D conversion can be
forcibly terminated.
0
R/W Ladder Resistance Select
0: Ladder resistance operates while the A/D converter
is idle.
1: Ladder resistance is halted while the A/D converter
is idle.
The ladder resistance is always halted in standby
mode, watch mode, or module standby mode, and at a
reset.
All 1 
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 3.00 May 15, 2007 Page 352 of 516
REJ09B0152-0300