HD64F38602R Datasheet, PDF (91/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.8.2 Notes on Switching Functions of External Interrupt Pins
When PFCR and PMRB are rewritten to switch the functions of external interrupt pins and when
the value of the ECPWME bit in AEGSR is rewritten to switch between selection and non-
selection of IRQAEC, the following points should be observed.
When a pin function is switched by rewriting PFCR or PMRB that controls an external interrupt
pin (IRQAEC, IRQ1, or IRQ0), the interrupt request flag is set to 1 at the time the pin function is
switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to
0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets
selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even
if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC).
Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function.
Figure 3.7 shows the procedure for setting a bit in PFCR and PMRB and clearing the interrupt
request flag. This procedure also applies to AEGSR setting.
When switching a pin function, mask the interrupt before setting the bit in PFCR and PMRB (or
AEGSR). After accessing PFCR and PMRB (or AEGSR), execute at least one instruction (e.g.,
NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is
executed immediately after PFCR and PMRB (or AEGSR) access without executing an
instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level. However, the procedure in figure 3.7 is
recommended because IECPWM is an internal signal and determining its value is complicated.
I bit in CCR ← 1
Set PFCR and PMRB (or AEGSR) bit
Execute NOP instruction
Clear interrupt request flag to 0
Interrupts masked. (Another possibility
is to disable the relevant interrupt in the
interrupt enable register 1.)
After setting PFCR and PMRB
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
I bit in CCR← 0
Interrupt mask cleared
Figure 3.7 PFCR and PMRB (or AEGSR) Setting
and Interrupt Request Flag Clearing Procedure
Rev. 3.00 May 15, 2007 Page 59 of 516
REJ09B0152-0300