HD64F38602R Datasheet, PDF (214/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
5. When an input capture function is specified, inputting a valid edge to the FTIOA to FTIOD
pins sets the status bit of the corresponding TSRW, even if the CTS bit in TMRW is 0
(counting disabled state). When the relevant interrupt is enabled, this inputting generates an
interrupt.
6. When the input capture timing conflicts with the corresponding GRA to GRD write timing,
a. the written values are reflected in GRA to GRD.
b. the status flag of the corresponding TSRW is set.
7. When the input capture timing conflicts with the GRA to GRD read timing, the read values are
ones before capturing. The captured values can be read one clock after the capturing.
8. When the input capture A or B conflicts with the GRC or GRD write timing as the input
capture operation in buffer mode,
a. the captured values are reflected in GRA or GRB.
b. the written values are reflected in GRC or GRD. (The values in GRC or GRD are not ones
in GRA or GRB before capturing.)
9. When the compare match timing conflicts with the GRA to GRD write timing as the compare
match operation,
a. the written values are reflected in GRA to GRD.
b. the FTIOA to FTIOD output changes by the compare match.
10. When the compare match A or B conflicts with the GRA or GRB write timing as the compare
match operation in buffer mode,
a. the written values are reflected in GRA or GRB. (The values in GRA or GRB are not ones
in GRC or GRD of the buffer register.)
b. the FTIOA or FTIOB output changes by the compare match.
11. When the compare match A or B conflicts with the GRC or GRD write timing as the compare
match operation in buffer mode,
a. the values in GRA or GRB are ones in GRC or GRD before writing.
b. the FTIOA or FTIOB output changes by the compare match.
12. When GRC or GRD is specified to the compare match output as the compare match operation
in buffer mode, FTIOC or FTIOD output changes by the GRC or GRD compare match.
13. When φw, φw/4, φw/16, or FTCI input is selected as the count clock, counting is enabled even
in subactive and subsleep modes. Counting is disabled during the oscillation stabilization time
in transition to the active mode.
14. When φw, φw/4, φw/16, or FTCI input is selected as the count clock, counting is enabled in
active and sleep modes although counting may be misaligned by one in transition from the
active to subactive mode.
Rev. 3.00 May 15, 2007 Page 182 of 516
REJ09B0152-0300