HD64F38602R Datasheet, PDF (344/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
Output
SCL
control
Noise canceler
SDA
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
Bus state
decision circuit
Arbitration
decision circuit
[Legend]
ICCR1 : I²C bus control register 1
ICCR2 : I²C bus control register 2
ICMR : I²C bus mode register
ICSR : I²C bus status register
ICIER : I²C bus interrupt enable register
ICDRT : I²C bus transmit data register
ICDRR : I²C bus receive data register
ICDRS : I²C bus shift register
SAR : Slave address register
ICIER
ICSR
Interrupt
generator
Figure 16.1 Block Diagram of I²C Bus Interface 2
Interrupt
request
Rev. 3.00 May 15, 2007 Page 312 of 516
REJ09B0152-0300