HD64F38602R Datasheet, PDF (311/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.5
Note on Switching SCK3 Pin Function
If the SCK3 pin is used as a clock output pin by the SCI3 in clock synchronous mode and is then
switched to a general input/output pin (a pin with a different function), the SCK3 pin outputs a
low level signal for half a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
(1) When SCK3 Pin Function is Switched from Clock Output to Non Clock-Output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR to 1 and 0, respectively.
In this case, bit COM in SMR should be left 1. The above prevents the SCK3 pin from being used
as a general input/output pin. To avoid an intermediate level of voltage from being applied to the
SCK3 pin, the line connected to the SCK3 pin should be pulled up to the V_CC level via a resistor, or
supplied with output from an external device.
(2) When SCK3 Pin Function is Switched from Clock Output to General Input/Output
When stopping data transfer,
1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1
and 0, respectively.
2. Clear bit COM in SMR to 0
3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an
intermediate level of voltage from being applied to the SCK3 pin.
14.8.6 Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet
been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably,
you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not
two or more times).
Rev. 3.00 May 15, 2007 Page 279 of 518
REJ09B0152-0300