HD64F38602R Datasheet, PDF (530/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
5.2.2 Standby Mode
5.2.3 Watch Mode
5.2.4 Subsleep Mode
5.2.5 Subactive Mode
Page Revisions (See Manual for Details)
88 Modified
… However, as long as the rated voltage is supplied,
the contents of CPU registers, on-chip RAM, and some
on-chip peripheral module registers are retained. …
Modified
… or the requested interrupt is disabled by the interrupt
enable bit.
When a reset source is generated in standby mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes and the t_REL period has
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
88 Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in watch mode, the
system clock oscillator starts. If a reset is generated by
the RES pin, it must be kept low until the system clock
oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
89 Modified
… or the requested interrupt is disabled by the interrupt
enable register.
When a reset source is generated in subsleep mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes. The CPU starts reset
exception handling when the RES pin is driven high.
89 Modified
… on the combination of bits SSBY, LSON, and TMA3
in SYSCR1 and bits MSON and DTON in SYSCR2.
Subactive mode is not cleared if the I bit in CCR is set
to 1 or the requested interrupt is disabled by the
interrupt enable register.
When a reset source is generated in subactive mode,
the system clock oscillator starts. If a reset is generated
by the RES pin, it must be kept low until the system
clock oscillator output stabilizes and the t period has
REL
elapsed. The CPU starts reset exception handling
when the RES pin is driven high.
Rev. 3.00 May 15, 2007 Page 498 of 516
REJ09B0152-0300