HD64F38602R Datasheet, PDF (40/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
• Power-down state
Transition to power-down state by SLEEP instruction
2.1 Address Space and Memory Map
The address space of this LSI is 64 Kbytes, which includes the program area and the data area.
Figure 2.1 shows the memory map.
H'0000
H'0050
HD64F38602R
(Flash memory version)
Interrupt vector
H'3FFF
On-chip ROM
(16 Kbytes)
H'0000
H'0050
HD64338602R
(Masked ROM version)
Interrupt vector
H'3FFF
On-chip ROM
(16 Kbytes)
H'0000
H'0050
HD64338600R
(Masked ROM version)
Interrupt vector
H'1FFF
On-chip ROM
(8 Kbytes)
Not used
Not used
Not used
H'F020
Internal I/O registers
H'F100
H'F020
Internal I/O registers
H'F100
H'F020
Internal I/O registers
H'F100
Not used
Not used
Not used
H'FB80
H'FF80
On-chip RAM
(1 Kbyte)
Internal I/O registers
H'FFFF
H'FB80
H'FF80
On-chip RAM
(1 Kbyte)
Internal I/O registers
H'FD80
H'FF80
On-chip RAM
(512 bytes)
Internal I/O registers
H'FFFF
H'FFFF
Figure 2.1 Memory Map
Rev. 3.00 May 15, 2007 Page 8 of 516
REJ09B0152-0300