HD64F38602R Datasheet, PDF (327/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.3 Relationship between Data Input/Output and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a
combination of the MSS bit in SSCRH and the SSUMS bit in SSCRL. It also changes by the
BIDE bit in SSCRH. Figure 15.3 shows the relationship.
(1) When SSUMS = 0:
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
Shift register
(SSTRSR)
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
(4) When SSUMS = 1 and BIDE = 1:
Shift register
(SSTRSR)
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
Figure 15.3 Relationship between Data Input/Output Pin and Shift Register
Rev. 3.00 May 15, 2007 Page 295 of 518
REJ09B0152-0300