HD64F38602R Datasheet, PDF (270/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Initial
Bit
Bit Name Value R/W Description
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, Bit
TDRE in SSR is cleared to 0 and serial data
transmission is started. Be sure to carry out SMR
settings, and setting of bit SPC3 in SPCR, to decide the
transmission format before setting bit TE to 1.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clock synchronous mode. Be sure to carry
out the SMR settings to decide the reception format
before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state
3
MPIE
0
R/W Reserved
2
TEIE
0
R/W Transmit End Interrupt Enable
When this bit is set to 1, the TEI3 interrupt request is
enabled. TEI3 can be released by clearing bit TDRE to
0 and clearing bit TEND to 0 in SSR, or by clearing bit
TEIE to 0.
Rev. 3.00 May 15, 2007 Page 238 of 516
REJ09B0152-0300