HD64F38602R Datasheet, PDF (129/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.6 Usage Notes
5.6.1 Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while the SSBY and TMA3 bits in SYSCR1 and the LSON bit in SYSCR1 are cleared to 0,
a transition is made to standby mode. At the same time, pins go to the high-impedance state
(except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the timing in this
case.
φ
Internal data bus
Pins
SLEEP instruction fetch Next instruction fetch
Internal
SLEEP instruction execution processing
Port output
High-impedance
Active (high-speed) mode or active (medium-speed) mode
Standby mode
Figure 5.2 Standby Mode Transition and Pin States
5.6.2 Notes on External Input Signal Changes before/after Standby Mode
(1) When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as NMI, IRQ0, IRQ1, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φ_SUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in (3), Recommended Timing of External Input Signals, below.
Rev. 3.00 May 15, 2007 Page 97 of 516
REJ09B0152-0300