HD64F38602R Datasheet, PDF (329/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.5 Operation in Clocked Synchronous Communication Mode
Initialization in Clocked Synchronous Communication Mode: Figure 15.4 shows the
initialization in clocked synchronous communication mode. Before transmitting and receiving
data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
Note:
When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSCRL to 0
Clear CPOS and CPHS bits to 0 and set
MLS and CKS2 to CKS0 bits in SSMR
Set SCKS bit in SSCRH to 1
and set MSS and SOOS bits
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1
and set RIE, TIE, TEIE, and RSSTP
bits according to transmission/
reception/transmission and reception
End
Figure 15.4 Initialization in Clocked Synchronous Communication Mode
Rev. 3.00 May 15, 2007 Page 297 of 518
REJ09B0152-0300