HD64F38602R Datasheet, PDF (316/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Internal clock
SSCK
SCS
Multiplexer
Transmission/
reception
control circuit
SSO
SSI
Selector
SSMR
SSCRL
SSCRH
SSER
SSSR
SSTDR
SSTRSR
SSRDR
[Legend]
SSMR: SS mode register
SSCRL: SS control register L
SSCRH: SS control register H
SSER: SS enable register
SSSR: SS status register
SSTDR: SS transmit data register
SSTRSR: SS shift register
SSRDR: SS receive data register
Interrupt request
(TXI, TEI, RXI, OEI, CEI)
Figure 15.1 Block Diagram of SSU
15.2 Input/Output Pins
Table 15.1 shows the pin configuration of the SSU.
Table 15.1 Pin Configuration
Pin Name
SSU clock
SSU data input/output
SSU data input/output
SSU chip select input/output
Abbreviation I/O
SSCK
I/O
SSI
I/O
SSO
I/O
SCS
I/O
Function
SSU clock input/output
SSU data input/output
SSU data input/output
SSU chip select input/output
Rev. 3.00 May 15, 2007 Page 284 of 516
REJ09B0152-0300