HD64F38602R Datasheet, PDF (122/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.2.6 Active (Medium-Speed) Mode
In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the
system clock, and the CPU and on-chip peripheral modules function.
Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed)
mode is cleared, a transition to standby mode is made depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the
combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made
depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to
active (high-speed) mode or subactive mode is made by a direct transition. When the RES pin
goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared.
Rev. 3.00 May 15, 2007 Page 90 of 516
REJ09B0152-0300