HD64F38602R Datasheet, PDF (309/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8 Usage Notes
14.8.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD3 pin
value directly. In a break, the input from the RXD3 pin becomes all 0, setting the FER flag, and
possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
14.8.2 Mark State and Break Sending
When the SPC3 bit in SPCR is 0, the TXD3 pin functions as an I/O port whose direction (input or
output) and level are determined by PCR and PDR, regardless of the TE setting. This can be used
to set the TXD3 pin to the mark state (high level) or send a break during data transmission. To
maintain the communication line at the mark state until the SPC3 bit in SPCR is set to 1, set both
PCR and PDR to 1. As the SPC3 bit in SPCR is cleared to 0 at this point, the TXD3 pin functions
as an I/O port, and 1 is output from the TXD3 pin. To send a break during data transmission, first
set PCR to 1 and PDR to 0, and then clear the SPC3 and TE bits to 0. When the TE bit is cleared
to 0 directly after the SPC3 bit is cleared to 0, the transmitter is initialized regardless of the current
transmission state after the TE bit is cleared, the TXD3 pin functions as an I/O port after the SPC3
bit is cleared, and 0 is output from the TXD3 pin.
14.8.3
Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 3.00 May 15, 2007 Page 277 of 518
REJ09B0152-0300