HD64F38602R Datasheet, PDF (322/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.3.4 SS Enable Register (SSER)
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Initial
Bit
Bit Name Value R/W Description
7
TE
0
R/W Transmit enable
When this bit is 1, transmit operation is enabled.
6
RE
0
R/W Receive enable
When this bit is 1, receive operation is enabled.
5
RSSTP 0
R/W Receive single stop
When this bit is 1, receive operation is completed after
receiving one byte.
4
—
0
—
Reserved
This bit is always read as 0.
3
TEIE
0
R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
1
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, an RXI and an OEI interrupt
requests are enabled.
0
CEIE
0
R/W Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
Rev. 3.00 May 15, 2007 Page 290 of 516
REJ09B0152-0300