HD64F38602R Datasheet, PDF (317/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3 Register Descriptions
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS receive data register (SSRDR)
• SS transmit data register (SSTDR)
• SS shift register (SSTRSR)
Section 15 Synchronous Serial Communication Unit (SSU)
15.3.1 SS Control Register H (SSCRH)
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Initial
Bit
Bit Name Value R/W Description
7
MSS
0
R/W Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically
cleared.
0: Operates as a slave device
1: Operates as a master device
6
BIDE
0
R/W Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 15.4.3, Relationship between Data
Input/Output and Shift Register. When the SSUMS bit in
SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
two pins.
1: Bidirectional mode. Communication is performed by
using only one pin.
Rev. 3.00 May 15, 2007 Page 285 of 518
REJ09B0152-0300