HD64F38602R Datasheet, PDF (239/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
12.2.4 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Initial
Bit
Bit Name Value R/W Description
7 to 4 
All 1

Reserved
These bits are always read as 1.
3
CKS3
0
R/W Clock Select 3 to 0
2
CKS2
0
R/W Select the clock to be input to TCWD.
1
CKS1
0
R/W 00xx: On-chip oscillator: counts on R_OSC/2048
0
CKS0
0
R/W 0100: Internal clock: counts on φ /16
W
0101: Internal clock: counts on φ_W/256
011x: Reserved
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
For the on-chip oscillator overflow periods, see section
21, Electrical Characteristics.
In active (medium-speed), sleep (medium-speed),
subactive, and subsleep modes, the 00xx value and the
interval timer mode cannot be set simultaneously.
In subactive and subsleep modes, when the subclock
frequency is φ /8, the 010x value and the interval timer
W
mode cannot be set simultaneously.
[Legend] x: Don't care.
Rev. 3.00 May 15, 2007 Page 207 of 518
REJ09B0152-0300