HD64F38602R Datasheet, PDF (78/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.3 Input/Output Pins
Table 3.3 shows the pin configuration of the interrupt controller.
Table 3.3 Pin Configuration
Name
NMI
IRQAEC
IRQ1
IRQ0
I/O
Input
Input
Input
Input
Function
Nonmaskable external interrupt pin
Rising or falling edge can be selected
Maskable external interrupt pin
Rising, falling, or both edges can be selected
Maskable external interrupt pins
Rising or falling edge can be selected
3.4 Register Descriptions
The interrupt controller has the following registers.
• Interrupt edge select register (IEGR)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt flag register 1 (IRR1)
• Interrupt flag register 2 (IRR2)
Rev. 3.00 May 15, 2007 Page 46 of 516
REJ09B0152-0300