HD64F38602R Datasheet, PDF (503/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Appendix
Instruction Mnemonic
Instruction Branch
Stack
Fetch
Addr. Read Operation
I
J
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBX
SUBX #xx:8, Rd
1
SUBX. Rs, Rd
1
TRAPA
TRAPA #xx:2
2
1
2
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC
XORC #xx:8, CCR
1
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. It cannot be used in this LSI.
Rev. 3.00 May 15, 2007 Page 471 of 516
REJ09B0152-0300