HD64F38602R Datasheet, PDF (254/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
13.3.6 Event Counter H (ECH)
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH
also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination
with ECL.
Initial
Bit Bit Name Value R/W Description
7
ECH7
0
6
ECH6
0
5
ECH5
0
4
ECH4
0
R Either the external asynchronous event AEVH pin, φ/2,
R
φ/4, or φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source.
R
ECH can be cleared to H'00 when the CRCH bit in
R
ECCSR is cleared to 0.
3
ECH3
0
R
2
ECH2
0
R
1
ECH1
0
R
0
ECH0
0
R
13.3.7 Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL
also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination
with ECH.
Initial
Bit Bit Name Value R/W Description
7
ECL7
0
6
ECL6
0
5
ECL5
0
4
ECL4
0
R Either the external asynchronous event AEVL pin, φ/2,
R
φ/4, or φ/8 can be selected as the input clock source.
ECL can be cleared to H'00 when the CRCL bit in
R
ECCSR is cleared to 0.
R
3
ECL3
0
R
2
ECL2
0
R
1
ECL1
0
R
0
ECL0
0
R
Rev. 3.00 May 15, 2007 Page 222 of 516
REJ09B0152-0300