HD64F38602R Datasheet, PDF (242/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
12.4 Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF
flag must be cleared to 0 in the interrupt handling routine.
12.5 Usage Notes
12.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode
If modes are switched between watchdog timer and interval timer, while the WDT is operating, an
error may occur in the count value. Software must stop the watchdog timer (by clearing the
WDON bit to 0) before switching modes.
12.5.2 Module Standby Mode Control
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register
WD1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is
set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter
module standby mode but continues operating. When the WDON bit is cleared to 0 by software
after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the
watchdog timer enters module standby mode.
12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0
When clearing the WT/IT or IEOVF bit in the timer control/status register WD2 (TCSRWD2) to
0, the corresponding bit may not be cleared to 0 depending on the program address. In particular,
if lower two bits in the address of the MOV.B instruction to transfer a value to TCSRWD2 are
B'10, the WT/IT or IEOVF bit is successfully cleared to 0, whereas if lower two bits in the address
are B'00, the WT/IT or IEOVF bit may not be cleared to 0. To avoid this failure, make sure to use
the assembly program shown in table 12.1, when clearing the WT/IT or IEOVF bit to 0. Specify
TCSRWD2 by the 8-bit absolute address, and LABEL by the 16-bit absolute address. Don't
change nor add instructions. The value of "xx" in line 1 and line 4 must be set according to table
12.2. Use an arbitrary 8-bit general register for Rn and Rm. In addition, Address1 in table 12.1
shows an example when the WT/IT or IEOVF bit is cleared to 0 successfully by the MOV.B
instruction in line 2. Address2 in table 12.1 shows an example when the WT/IT or IEOVF bit fails
to be cleared to 0 by the MOV.B instruction in line 2, but cleared to 0 by the MOV.B instruction
in line 6.
Rev. 3.00 May 15, 2007 Page 210 of 516
REJ09B0152-0300