HD64F38602R Datasheet, PDF (84/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.5 Interrupt Sources
3.5.1 External Interrupts
There are four external interrupts: NMI, IRQAEC, IRQ1, and IRQ0.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of
the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested
at a rising edge or a falling edge on the NMI pin.
(2) IRQ1 and IRQ0 Interrupts
IRQ1 and IRQ0 interrupts are requested by input signals at IRQ1 and IRQ0 pins.
Using the IEG1 and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by
a rising or falling edge at IRQ1 and IRQ0 pins.
When the specified edge is input while the IRQ1 and IRQ0 pin functions are selected by PFCR
and PMRB, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated.
Clearing the IEN1 and IEN0 bits in IENR1 to 0 disables the interrupt request to be accepted.
Setting the I bit in CCR to 1 masks all interrupts.
(3) IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM
output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the
ECPWME bit in AEGSR to 0.
Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is
generated by a rising edge, falling edge, or both edges.
When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in
IRR1 is set to 1 and an interrupt request is generated. For details, see section 13, Asynchronous
Event Counter (AEC).
Rev. 3.00 May 15, 2007 Page 52 of 516
REJ09B0152-0300