HD64F38602R Datasheet, PDF (236/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
Initial
Bit
Bit Name Value R/W Description
2
WDON 1
R/W Watchdog Timer On
TCWD starts counting up when the WDON bit is set to 1
and halts when the WDON bit is cleared to 0.
[Setting condition]
• When 1 is written to the WDON bit and 0 to the B2WI
bit while the TCSRWE bit is 1
• Reset by RES pin
[Clearing conditions]
• When 0 is written to the WDON bit and 0 to the B2WI
bit while the TCSRWE bit is 1
1
B0WI
1
R/W Bit 0 Write Inhibit
The WRST bit can be written only when the write value of
the B0WI bit is 0. This bit is always read as 1.
0
WRST 0
R/W Watchdog Timer Reset
Indicates whether a reset caused by the watchdog timer
is generated. This bit is not cleared by a reset caused by
the watchdog timer.
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WRST bit and 0 to the B0WI
bit while the TCSRWE bit is 1
Rev. 3.00 May 15, 2007 Page 204 of 516
REJ09B0152-0300