HD64F38602R Datasheet, PDF (121/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules function except for the
IIC2. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM,
and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states
as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in subsleep mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t_REL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
5.2.5 Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules function
except for the IIC2. As long as a required voltage is applied, the contents of some registers of the
on-chip peripheral modules are retained.
Subactive mode is cleared by the SLEEP instruction. When subactive mode is cleared, a transition
to subsleep mode, active mode, or watch mode is made, depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2.
When a reset source is generated in subactive mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t_REL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
The operating frequency of subactive mode is selected from φ_W (watch clock), φ_W/2, φ_W/4, and φ_W/8
by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating
frequency changes to the frequency which is set before the execution.
Rev. 3.00 May 15, 2007 Page 89 of 516
REJ09B0152-0300