HD64F38602R Datasheet, PDF (76/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.2 Reset
A reset has the highest exception priority.
There are three sources to generate a reset. Table 3.2 lists the reset sources.
Table 3.2 Reset Sources
Reset Source
RES pin
Power-on reset circuit
Watchdog timer
Description
Low level input
When the power supply voltage (Vcc) rises
For details, see section 19, Power-On Reset Circuit.
When the counter overflows
For details, see section 12, Watchdog Timer.
3.2.1 Reset Exception Handling
When a reset source is generated, all the processing in execution is terminated and this LSI enters
the reset state. The internal state of the CPU and the registers of the on-chip peripheral modules
are initialized by a reset.
To ensure that this LSI is reset, handle the RES pin as shown below.
• When power is supplied, or the system clock oscillator is stopped
Hold the RES pin low until oscillation of the system clock oscillator has stabilized.
• When the system clock oscillator is operating
Hold the RES pin low for the t_REL state, which is specified as the electrical characteristics.
After a reset source is generated, this LSI starts reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, and the I bit in CCR is set to 1.
2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the
PC, and then program execution starts from the address indicated by the PC.
The reset exception handling sequence by the RES pin is shown in figure 3.1.
Rev. 3.00 May 15, 2007 Page 44 of 516
REJ09B0152-0300