HD64F38602R Datasheet, PDF (83/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.4.5 Interrupt Flag Register 2 (IRR2)
IRR2 indicates the interrupt request status of the A/D converter, timer B1, and asynchronous event
counter.
Initial
Bit
Bit Name Value R/W Description
7

0

Reserved
The write value should always be 0.
6
IRRAD 0
R/(W)* A/D Converter Interrupt Request Flag
[Setting condition]
When A/D conversion ends
[Clearing condition]
When 0 is written to this bit
5 to 3 
All 0

Reserved
The write value should always be 0.
2
IRRTB1 0
R/(W)* Timer B1 Interrupt Request Flag
[Setting condition]
When the timer B1 compare match or overflow occurs
[Clearing condition]
When 0 is written to this bit
1

0

Reserved
The write value should always be 0.
0
IRREC 0
R/(W)* Asynchronous Event Counter Interrupt Request Flag
[Setting condition]
When the asynchronous event counter overflows
[Clearing condition]
When 0 is written to this bit
Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 51 of 516
REJ09B0152-0300