HD64F38602R Datasheet, PDF (208/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
10.5.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,
FTIOB, FTIOC, or FTIOD).
When TCNT matches GR, the compare match signal is generated only after the next counter clock
pulse is input.
Figure 10.16 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
FTIOA to FTIOD
Figure 10.16 Output Compare Output Timing
Rev. 3.00 May 15, 2007 Page 176 of 516
REJ09B0152-0300