HD64F38602R Datasheet, PDF (64/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φ_SUB). The period from a rising
edge of φ or φ_SUB to the next rising edge is called one state. A bus cycle consists of two states.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
φ or φ _SUB
Internal address bus
Bus cycle
T₁ state
T₂ state
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
Rev. 3.00 May 15, 2007 Page 32 of 516
REJ09B0152-0300