HD64F38602R Datasheet, PDF (269/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Initial
Bit
Bit Name Value R/W Description
1
CKS1
0
R/W Clock Select 0 and 1
0
CKS0
0
R/W These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ_W clock (n = 0)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 01 in subactive mode or
subsleep
mode,
the
SCI3
can
be
used
only
when
φ
W
is
selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6 Serial Control Register (SCR)
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer
clock source. For details on interrupt requests, refer to section 14.7, Interrupt Requests.
SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Initial
Bit
Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI3 interrupt request is
enabled. TXI3 can be released by clearing the TDRE it
or TI bit to 0.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, the RXI3 and ERI3 interrupt
requests are enabled.
RXI3 and ERI3 can be released by clearing the RDRF
bit or the FER, PER, or OER error flag to 0, or by
clearing the RIE bit to 0.
Rev. 3.00 May 15, 2007 Page 237 of 518
REJ09B0152-0300