HD64F38602R Datasheet, PDF (130/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
(2) When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active mode or subactive mode, after oscillation is started by an
interrupt via a different signal, the external input signal cannot be captured if the high-level width
at that point is less than 2 tcyc or 2 . tsubcyc
(3) Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at
least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as
shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case 2"
and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Operating mode
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Standby mode or
watch mode
Wait for osc-
illation
stabilization
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible: case 1
Capture possible: case 2
Capture possible: case 3
Capture not possible
Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes
before/after Standby Mode or Watch Mode
(4) Input Pins to which these Notes Apply
NMI, IRQ0, IRQ1, IRQAEC, and ADTRG
Rev. 3.00 May 15, 2007 Page 98 of 516
REJ09B0152-0300