HD64F38602R Datasheet, PDF (273/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Initial
Bit
Bit Name Value R/W Description
5
OER
0
R/(W)* Overrun Error
[Setting condition]
• When an overrun error occurs in reception
[Clearing condition]
• When 0 is written to OER after reading OER = 1
When bit RE in SCR is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with bit OER set to 1, and in clock
synchronous mode, transmission cannot be continued
either.
4
FER
0
R/(W)* Framing Error
[Setting condition]
• When a framing error occurs in reception
[Clearing condition]
• When 0 is written to FER after reading FER = 1
When bit RE in SCR is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked. When a framing error occurs, the receive data
is transferred to RDR but bit RDRF is not set.
Reception cannot be continued with bit FER set to 1. In
clock synchronous mode, neither transmission nor
reception is possible when bit FER is set to 1.
Rev. 3.00 May 15, 2007 Page 241 of 518
REJ09B0152-0300