HD64F38602R Datasheet, PDF (336/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.7 Initialization in Four-Line Bus Communication Mode
Figure 15.10 shows the initialization in four-line bus communication mode. Before transmitting
and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be
initialized.
Note:
When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSCRL to 1
[1]
Set MLS in SSMR to 1 and
set CPOS, CPHS, and
CKS2 to CKS0
[2]
Set SCKS in SSCRH to 1 and
set BIDE, MSS, SOOS, CSS1,
and CSS0
[1] The MLS bit is set to 1 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.
[2] In bidirectional mode, the BIDE bit is set
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and
set RIE, TIE, TEIE, and RSSTP
according to transmission/reception/
transmission and reception
End
Figure 15.10 Initialization in Four-Line Bus Communication Mode
Rev. 3.00 May 15, 2007 Page 304 of 516
REJ09B0152-0300