HD64F38602R Datasheet, PDF (24/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............ 254
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 258
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 259
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 260
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 262
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ..................... 263
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ..................... 264
Figure 14.9 Data Format in Clock Synchronous Communication.............................................. 265
Figure 14.10 Example of SCI3 Operation in Transmission in
Clock Synchronous Mode ..................................................................................... 266
Figure 14.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) .................... 267
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode................... 268
Figure 14.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 269
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and
Receive Operations (Clock Synchronous Mode) .................................................. 270
Figure 14.15 IrDA Block Diagram............................................................................................. 271
Figure 14.16 IrDA Transmission and Reception ........................................................................ 272
Figure 14.17 (a) RDRF Setting and RXI Interrupt ..................................................................... 276
Figure 14.17 (b) TDRE Setting and TXI Interrupt ..................................................................... 276
Figure 14.17 (c) TEND Setting and TEI Interrupt...................................................................... 276
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode ...................................... 278
Figure 14.19 Relation between RDR Read Timing and Data..................................................... 280
Section 15 Synchronous Serial Communication Unit (SSU)
Figure 15.1 Block Diagram of SSU............................................................................................ 284
Figure 15.2 Relationship between Clock Polarity and Phase, and Data ..................................... 294
Figure 15.3 Relationship between Data Input/Output Pin and Shift Register ............................ 295
Figure 15.4 Initialization in Clocked Synchronous Communication Mode................................ 297
Figure 15.5 Example of Operation in Data Transmission .......................................................... 298
Figure 15.6 Sample Serial Transmission Flowchart ................................................................... 299
Figure 15.7 Example of Operation in Data Reception (MSS = 1) .............................................. 300
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)....................................................... 301
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations.............................. 302
Figure 15.10 Initialization in Four-Line Bus Communication Mode ......................................... 304
Figure 15.11 Example of Operation in Data Transmission (MSS = 1)....................................... 306
Figure 15.12 Example of Operation in Data Reception (MSS = 1) ............................................ 308
Figure 15.13 Arbitration Check Timing ..................................................................................... 309
Rev. 3.00 May 15, 2007 Page xxiv of xxxii