HD64F38602R Datasheet, PDF (251/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
13.3.4 Event Counter Control Register (ECCR)
ECCR controls the counter input clock and PWM clock.
Initial
Bit Bit Name Value R/W Description
7
ACKH1
0
R/W AEC Clock Select H
6
ACKH0
0
R/W Select the clock used by ECH.
00: AEVH pin input
01: φ/2
10: φ/4
11: φ/8
5
ACKL1
0
R/W AEC Clock Select L
4
ACKL0
0
R/W Select the clock used by ECL.
00: AEVL pin input
01: φ/2
10: φ/4
11: φ/8
3
PWCK2 0
R/W Event Counter PWM Clock Select
2
PWCK1 0
R/W Select the event counter PWM clock.
1
PWCK0 0
R/W 000: φ/2
001: φ/4
010: φ/8
011: φ/16
100: φ/32
101: φ/64
110: φ /16
W
111: Setting prohibited
When changing the event counter PWM clock, the
ECPWME bit in AEGSR must be cleared to 0 to stop
the PWM before rewriting this setting.
0

0
R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.
Rev. 3.00 May 15, 2007 Page 219 of 516
REJ09B0152-0300