HD64F38602R Datasheet, PDF (119/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
3. Functions if φ , φ /4, or φ /16 is selected as an internal clock. Halted and retained
WW
W
otherwise.
4. Functions if the on-chip oscillator is selected. Halted and retained otherwise.
5. Functions if the on-chip oscillator is selected or if φ_W/16 or φ_W/256 is selected as an
internal clock. Halted and retained otherwise.
6. Functions if the 32.768-kHz RTC is selected as an internal clock. Halted and retained
otherwise.
7. Functions if φ is selected as an internal clock. Halted and retained otherwise.
W
8. Functions if φ_SUB/2 is selected as an internal clock. Halted and retained otherwise.
9. Functions if φ /2 is selected as an internal clock. Halted and retained otherwise.
W
5.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and
on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral
modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
Rev. 3.00 May 15, 2007 Page 87 of 516
REJ09B0152-0300