HD64F38602R Datasheet, PDF (379/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.7 Usage Notes
16.7.1
Note on Issuing Stop Condition and Start (Re-Transmit) Condition
The stop condition or start (re-transmit) condition should be issued after recognizing the falling
edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the
SCLO bit in the I2C control register 2 (ICCR2). Note that if the stop condition or start (re-
transmit) condition is issued in a particular timing and the situations shown below, these
conditions may not correctly output.
1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load
capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit.
2. When the slave device elongates the low level period between the eighth and ninth clocks and
activates the bit synchronous circuit.
16.7.2
Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)
The WAIT bit in the I²C bus mode register (ICMR) should be set to 0. Note that if the WAIT bit is
set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during
the eighth clock, the high level period of the ninth clock may be shorter than a given period.
16.7.3
Restriction on Transfer Rate Setting in Multimaster Operation
In multimaster operation, if the IIC transfer rate setting in this LSI is slower than those of the other
masters, SCL may be output with an unexpected width. To avoid this phenomenon, set the transfer
rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer
rate of the other masters is set to 400 kbps, the IIC transfer rate in this LSI should be set to 223
kbps (= 400/1.18) or more.
Rev. 3.00 May 15, 2007 Page 347 of 516
REJ09B0152-0300