HD64F38602R Datasheet, PDF (538/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
14.3.6 Serial Control Register
(SCR)
14.3.7 Serial Status Register
(SSR)
14.3.10 IrDA Control Register
(IrCR)
Page Revisions (See Manual for Details)
237 Bit 3 is reserved.
240 Deleted
SSR consists of status flags of the SCI3 and
multiprocessor bits for transfer. 1 cannot be written to
flags TDRE, RDRF, OER, PER, and FER; they can only
be cleared.
240 Bits 1 and 0 are reserved.
252 Modified
Bit Bit Name Description
7 IrE
IrDA EnableSelects whether the SCI3 I/O pins
function as the SCI3 or IrDA.0: TXD3/IrTXD and
RXD3/IrRXD pins function as TXD3 and RXD31:
TXD3/IrTXD and RXD3/IrRXD pins function as
IrTXD and IrRXD
14.3.11 Serial Extended Mode
Register (SEMR)
253
Added
Bit Bit Name Description
3 ABCS Asynchronous Mode Basic Clock Select
Selects the basic clock for the bit period in
asynchronous mode.
This setting is enabled only in asynchronous mode
(COM bit in SMR3 is 0).
0: Operates on a basic clock with a frequency of
16 times the transfer rate
1: Operates on a basic clock with a frequency of
eight times the transfer rate
Clear the ABCS bit to 0, when the IrDA function is
enabled.
Table 14.8 Data Transfer Formats 255
(Asynchronous Mode)
Table 14.9 SMR Settings and 256
Corresponding Data Transfer
Formats
The formats are modified.
The settings are modified.
Rev. 3.00 May 15, 2007 Page 506 of 516
REJ09B0152-0300