HD64F38602R Datasheet, PDF (250/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
13.3.3 Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins, and
controls IRQAEC/IECPWM.
Initial
Bit Bit Name Value R/W Description
7
AHEGS1
0
R/W AEC Edge Select H
6
AHEGS0
0
R/W Select rising, falling, or both edge sensing for the AEVH
pin.
00: Falling edge on AEVH pin is sensed
01: Rising edge on AEVH pin is sensed
10: Both edges on AEVH pin are sensed
11: Setting prohibited
5
ALEGS1
0
R/W AEC Edge Select L
4
ALEGS0
0
R/W Select rising, falling, or both edge sensing for the AEVL
pin.
00: Falling edge on AEVL pin is sensed
01: Rising edge on AEVL pin is sensed
10: Both edges on AEVL pin are sensed
11: Setting prohibited
3
AIEGS1
0
R/W IRQAEC Edge Select
2
AIEGS0
0
R/W Select rising, falling, or both edge sensing for the
IRQAEC pin.
00: Falling edge on IRQAEC pin is sensed
01: Rising edge on IRQAEC pin is sensed
10: Both edges on IRQAEC pin are sensed
11: Setting prohibited
1
ECPWME 0
R/W Event Counter PWM Enable
Controls operation of event counter PWM and selection
of IRQAEC.
0: AEC PWM halted, IRQAEC selected
1: AEC PWM enabled, IRQAEC not selected
0

0
R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.
Rev. 3.00 May 15, 2007 Page 218 of 516
REJ09B0152-0300