HD64F38602R Datasheet, PDF (340/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0:
SCS
(output)
SSCK
(Hi-Z)
SSI
RDRF
Bit 7
One frame
Bit 0
Bit 7
One frame
Bit 0
Bit 7
Bit 0
RSSTP
LSI operation
RXI generated
RXI generated
RXI generated
User
Dummy read on SSRDR
processing
Read data in SSRDR Set RSSTP to 1Read data in SSRDR
(2) When CPOS = 0 and CPHS = 1:
SCS
(output)
SSCK
(Hi-Z)
SSI
RDRF
Bit 7
Bit 0
One frame
Bit 7
One frame
Bit 0
Bit 7
Bit 0
RSSTP
LSI operation
RXI generated
RXI generated
RXI generated
User
Dummy read on SSRDR
processing
Read data in SSRDR Set RSSTP to 1Read data in SSRDR
Figure 15.12 Example of Operation in Data Reception (MSS = 1)
Rev. 3.00 May 15, 2007 Page 308 of 516
REJ09B0152-0300