HD64F38602R Datasheet, PDF (310/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.18.
Thus, the reception margin in asynchronous mode is given by formula (1) below.

M = _(0.5 –

1 _)–
2N
D – 0.5
N
– (L – 0.5) F
× 100(%)
... Formula (1)
Where
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RXD3)
Synchronization
sampling timing
Start bit
D0
D1
Data sampling
timing
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode
Rev. 3.00 May 15, 2007 Page 278 of 516
REJ09B0152-0300