HD64F38602R Datasheet, PDF (126/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in
SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode
after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (6).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tsubcyc before transition) + (Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states) × (tcyc after transition)……………………….………………..(6)
Example: When φw/8 and φosc/8 are selected as the CPU operating clock before and after
the transition, respectively, and wait time = 8192 states
Direct transition time = (2 + 1) × 8tw + 8192 × 1tosc + 14 × 8tosc = 24tw + 8304tosc
For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 94 of 516
REJ09B0152-0300