HD64F38602R Datasheet, PDF (536/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Section 12 Watchdog Timer
12.2.1 Timer Control/Status
Register WD1 (TCSRWD1)
Page Revisions (See Manual for Details)
203 Added
Bit Bit Name Description
0 WRST Watchdog Timer Reset
Indicates whether a reset caused by the watchdog
timer is generated. This bit is not cleared by a reset
caused by the watchdog timer.
[Setting condition]
When TCWD overflows and an internal reset signal
is generated
12.3.1 Watchdog Timer Mode 208
Figure 12.2 Example of Watchdog 208
Timer Operation
Modified
… When a clock pulse is input after the TCWD count
value has reached H'FF, the watchdog timer overflows
and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles by
the on-chip oscillator (R ).
OSC
Modified
H'FF
H'F1
TCWD
count value
TCWD overflow
Figure 12.3 Interval Timer Mode 209
Operation
12.5.3 Clearing the WT/IT or
210
IEOVF Bit in TCSRWD2 to 0
Table 12.1 Assembly Program for 211
Clearing WT/IT or IEOVF Bit to 0
H'00
Start
H'F1 written
to TCWD
Internal reset
signal
H'F1 written to TCWD
Reset generated
512 clock cycles by R_osc
Modified
H'FF
TCWD
count value
H'00
Time
WT/IT = 1
Interval timer
Interval timer
Interval timer
Interval timer
Interval timer
interrupt
interrupt
interrupt
interrupt
interrupt
request generated request generated request generated request generated request generated
Added
Added
Rev. 3.00 May 15, 2007 Page 504 of 516
REJ09B0152-0300