SH7619_09 Datasheet, PDF (99/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
3.3.3 Write Access
Write Hit: In a write access in write-back mode, the data is written to the cache and no external
memory write cycle is generated. The U bit of the entry that has been written to is set to 1, and the
LRU bits are updated to indicate that the hit way is the most recently hit way. In write-through
mode, the data is written to the cache and an external memory write cycle is generated. The U bit
of the entry that has been written to is not updated, and the LRU bits are updated to indicate that
the hit way is the most recently hit way.
Write Miss: In write-back mode, an external write cycle starts when a write miss occurs, and the
entry is updated. The way to be replaced is shown in table 3.1. When the U bit of the entry which
is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been
transferred to the write-back buffer. Data is written to the cache and the U bit and the V bit are set
to 1. The LRU bits are updated to indicate that the replaced way is the most recently updated way.
After the cache has completed its update cycle, the write-back buffer writes the entry back to the
memory. Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write
miss; the write is only to the external memory.
3.3.4 Write-Back Buffer
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 3.3 shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address to be written to external memory
Longword 0 to 3: One line of cache data to be written to external memory
Figure 3.3 Write-Back Buffer Configuration
3.3.5 Coherency of Cache and External Memory
Coherency between the cache and the external memory must be ensured by software. When
memory shared by this LSI and another device is allocated to a cacheable address space, invalidate
and write back the cache by accessing the memory-mapped cache, as required. Memory that is
shared by the CPU, DMAC, and E-DMAC of this LSI should also be handled in this way.
Rev. 6.00 Jul. 15, 2009 Page 59 of 816
REJ09B0237-0600