SH7619_09 Datasheet, PDF (175/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W
19 to 15 
All 0 R
14
TED3
0
R/W
13
TED2
0
R/W
12
TED1
0
R/W
11
TED0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Delay from Address to RD or WE Assert
Specify the delay time from address output to RD or WE
assertion in PCMCIA interface.
0000: 0.5 cycles
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: Reserved (setting prohibited)
1001: Reserved (setting prohibited)
1010: Reserved (setting prohibited)
1011: Reserved (setting prohibited)
1100: Reserved (setting prohibited)
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 6.00 Jul. 15, 2009 Page 135 of 816
REJ09B0237-0600