SH7619_09 Datasheet, PDF (28/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 13.4 Changes in Channel Priority in Round-Robin Mode............................................... 347
Figure 13.5 Data Flow of Dual Address Mode........................................................................... 349
Figure 13.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory) ................................ 350
Figure 13.7 Data Flow in Single Address Mode......................................................................... 351
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode ................................. 352
Figure 13.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection) ........................................................ 353
Figure 13.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)....................................................... 354
Figure 13.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)....................................................... 354
Figure 13.12 Bus State when Multiple Channels are Operating................................................. 356
Figure 13.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 357
Figure 13.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 357
Figure 13.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 358
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 358
Figure 13.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection ................ 359
Figure 13.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ............................... 360
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When
DACK is Divided to 4 by Idle Cycles ................................................................... 362
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When
DACK is Divided to 2 by Idle Cycles ................................................................... 363
Figure 13.21 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When
DACK is Divided to 4 by Idle Cycles ................................................................... 363
Figure 13.22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When
DACK is Divided to 2 by Idle Cycles ................................................................... 364
Section 14 Compare Match Timer (CMT)
Figure 14.1 Block Diagram of Compare Match Timer............................................................... 367
Figure 14.2 Counter Operation ................................................................................................... 371
Figure 14.3 Count Timing .......................................................................................................... 371
Figure 14.4 Timing of CMF Setting ........................................................................................... 372
Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT...................... 373
Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 374
Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ....................... 375
Rev. 6.00 Jul. 15, 2009 Page xxvi of xxxviii