SH7619_09 Datasheet, PDF (475/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.5 SCIF Interrupts
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive-data-full (RXI), and break (BRI).
Table 15.11 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When TXI request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is
set to 1, a TXI interrupt request is generated.
When RXI request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXI
interrupt request is generated. The RXI interrupt request caused by DR flag is generated only in
asynchronous mode.
When BRI request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag in
SCLSR is set to 1, a BRI interrupt request is generated.
When ERI request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an ERI
interrupt request is generated.
When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERI interrupt and BRI
interrupt without requesting RXI interrupt.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 15.11 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
Description
Interrupt
Enable Bit
Interrupt initiated by receive error (ER)
RIE or REIE
Interrupt initiated by receive data FIFO full (RDF) or RIE
data ready (DR)
Interrupt initiated by break (BRK) or overrun error RIE or REIE
(ORER)
Interrupt initiated by transmit FIFO data empty
TIE
(TDFE)
Priority on
Reset Release
High
Low
Rev. 6.00 Jul. 15, 2009 Page 435 of 816
REJ09B0237-0600