SH7619_09 Datasheet, PDF (453/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.12 Line Status Register (SCLSR)
SCLSR is a 16-bit readable/writable register which can always be read from and written to by the
CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has
first been read (after being set to 1). SCLSR is initialized to H'0000 by a power-on reset.
Initial
Bit
Bit Name value R/W Description
15 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ORER
0
R/(W)* Overrun Error
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally *¹
[Clearing conditions]
• ORER is cleared to 0 when the chip is a power-on
reset
• ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
1: An overrun error has occurred *²
[Setting condition]
• ORER is set to 1 when the next serial receiving is
finished while receive FIFO data are full.
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ORER bit, which retains its
previous value.
2. The receive FIFO data register (SCFRDR)
hold the data before an overrun error is
occurred, and the next receive data is
extinguished. When ORER is set to 1,
SCIF can not continue the next serial
receiving.
Note: * The only value that can be written is 0 to clear the flag.
Rev. 6.00 Jul. 15, 2009 Page 413 of 816
REJ09B0237-0600